1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and more particularly to an overvoltage protection circuit of an output MOS transistor in a semiconductor integrated circuit.
2. Description of the Related Art
Conventionally, an overvoltage protection circuit is widely used to protect a transistor from an overvoltage such as serge voltage, and a dynamic clamping circuit is known as the overvoltage protection circuit disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 06-204410).
FIG. 1 shows the structure of such a dynamic clamping circuit, which is composed of a resistor 5, a MOS transistor 6, an output MOS transistor 7, a load 9, and a dynamic clamping circuit 10. As shown in FIG. 1, the output MOS transistor 7 and the load 9 are connected in series between a first power supply 1 and a second power supply 2 to form a N-channel source follower circuit structure. A node between the output MOS transistor 7 and the load 9 is connected with an output terminal 8. The output MOS transistor 7 is controlled to an ON/OFF state in response to a first control signal 3 supplied to a node A which is connected with the gate terminal i.e., a node B through a gate resistance 5. The first control signal 3 is an output voltage signal of a boosting circuit (not shown). The first control signal 3 has a signal of a voltage level higher than a voltage of the first power supply 1 when the output MOS transistor 7 is turned on, and has substantially the same voltage as a voltage of the second power supply 2 when the output MOS transistor 7 is turned off.
The MOS transistor 6 is connected between the node A and the output terminal 8 to discharge the gate charge of the output MOS transistor 7 when the output MOS transistor 7 is turned off. The MOS transistor 6 is controlled between the ON/OFF state in response to a second control signal 4 supplied to the gate terminal, i.e., a node C. The second control signal 4 has a substantially the same voltage as a voltage of the first power supply 1 when the MOS transistor 6 is turned on, and has substantially the same voltage as a voltage of the second power supply 2 when the MOS transistor 6 is turned off. When the first control signal 3 is in a high level, the second control signal 4 becomes in a low level. The reversal is true, too. The dynamic clamping circuit 10 is connected between the first power supply 1 and the node B. The dynamic clamping circuit 10 is composed of a zener diode D1 and diode D2 which are connected in series.
Next, the operation of the circuit will be described. When the output MOS transistor 7 should be turned off, the first control signal 3 is set to the low level and the second control signal 4 is set to the high level. At this time, the MOS transistor 6 is turned on such that the gate charge of the output MOS transistor 7 or the charge at the node B is discharged to the second power supply 2 through the output terminal 8 and the load 9. Also, a negative output voltage due to back electromotive force is generated at the output terminal 8 because of an inductance component of the load (inductance component of the inductive load such as a solenoid and a wire harness). In the high side switch for the automobile, a breakdown voltage of output MOS transistor 7 is set to 60 V or higher and a breakdown voltage of the dynamic clamping circuit 10 is set to about 40-60 V which is approximately equal to the breakdown voltage of the zener diode D1. When the applied voltage exceeds a breakdown voltage of the output MOS transistor 7, the output MOS transistor 7 breaks down and a breakdown current flows. Thus, there is a possibility that the output MOS transistor 7 degrades, if the overvoltage protection is not carried out by the dynamic clamping circuit 10. When a voltage higher than the breakdown voltage of the dynamic clamping circuit 10 is applied between the first power supply 1 and the output terminal 8 because of the negative output voltage generated at the output terminal 8, the voltage between the drain and the source in the output MOS transistor 7 is clamped to a breakdown voltage of the dynamic clamping circuit 10. With the negative output voltage, the design of the load is carried out such that the current flowing through the output MOS transistor 7 does not cross over a safe operation area when an overvoltage protection circuit operates. Therefore, there is no case that the output MOS transistor 7 is destroyed.
On the other hand, a positive voltage dump serge is generated at the first power supply 1 when a battery terminal is unfastened during the power generation by an alternator. If the dump serge is applied when the output MOS transistor 7 is in the off state, the dynamic clamping circuit 10 operates such that the dynamic clamping circuit 10 breaks down, like the case of the generation of the negative output voltage. At this time, the gate voltage rises so that the output MOS transistor 7 is turned on. As a result, the current flowing through the output MOS transistor 7 crosses over the safe operation area (SOA). Therefore, the output MOS transistor 7 is destroyed.
By the way, in the above-mentioned high side switch, the turn-on resistance of the output MOS transistor 7 is very small. The output MOS transistor 7 is formed from a set of cells as disclosed in Japanese Laid Open Patent Application (JP-P2002-343969A). As a method of accomplishing a low resistance, a method is used in which a cell size is shrunk to decrease the turn-on resistance per unit area. Through the cell shrinking, a phenomenon appears that the forward SOA is narrowed due to secondary breakdown in a state that a high voltage is applied between the drain and the source in the output MOS transistor 7. This gives a constraint to an overvoltage protection circuit operating in this area. Because the safe operation area becomes narrow, if the overvoltage protection circuit operates when an overvoltage of the dump serge is applied, the operation point crosses over the safe operation area so that the output MOS transistor 7 results in heat destruction. This phenomenon did not cause a problem in case of the output MOS transistor 7 having a wide safe operation area.
In conjunction with the above description, a drive circuit of a semiconductor switch is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 6-252721). In the drive circuit of this conventional example, a semiconductor switch controls supply of power to a load connected with a load drive power supply. A zener diode sets the semiconductor switch to an ON state based on the rise of a voltage between the semiconductor switch and the load when the semiconductor switch is turned off. A second semiconductor switch is connected in series with the zener diode. A short-circuit detection circuit is provided to turn off a second semiconductor switch based on a voltage between the semiconductor switch and the load because of the short-circuit of the zener diode.
Also, a high side switch circuit is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 8-8704). In the high side switch circuit of this conventional example, a boosting section supplies a first MOS transistor for a high side switch with a gate voltage obtained by boosting a power supply voltage. A serge detecting section detects a serge voltage higher than the maximum rating power supply voltage. A second MOS transistor is provided between a power supply terminal and the boosting section and is turned off based on the output of the serge detecting section. A resistance is provided between the gate of the second MOS transistor and the power supply terminal. A third MOS transistor is provided between the gate of the second MOS transistor and the ground. A voltage boosted by the boosting section is fed back to the gate of the second MOS transistor through a first diode. The output of the serge detecting section is connected with the gate of the third MOS transistor. When the second MOS transistor is turned off, the third MOS transistor is turned on.
Also, a semiconductor device is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 8-288817). In this conventional example, the semiconductor device is composed of a power MOSFET which has a drain connected with a power supply terminal and a source connected with an output terminal. A first MOSFET is arranged between the gate of the power MOSFET and the ground of the control circuit to turn off the power MOSFET based on a voltage of an input terminal. A second MOSFET is arranged between the gate of the power MOSFET and an output terminal to turn off the power MOSFET based on the voltage of the input terminal. A gate charging circuit is connected with the gate of the power MOSFET to turn on the power MOSFET based on the voltage of the input terminal.
Also, a protection circuit of a semiconductor device is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 9-163583). In an inverse bias safe operation area of an IGBT, a permission voltage is high in case of a current lower than the rating current of IGBT and the permission voltage decreases as the current becomes larger. Therefore, in this conventional example, at least two of clamp devices are connected in series between the collector and the gate in the IGBT. Switches are provided in parallel to the clam devices other than one clamp device. A switch control unit controls the switches based on a collector current detected by a detecting section. When the collector current of IGBT is as small as the rating current, the switches are opened such that all the clamp devices are connected between the collector and the gate of the IGBT. Thus, the clamp voltage of the IGBT is increased.
A load drive circuit which has a serge protection function is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 9-298834). In this conventional example, the load drive circuit has a serge protection function and is composed of an output transistor in which an emitter is grounded through a load and a collector is connected with a power supply line, and a control circuit section which controls a gate voltage of the output transistor to carry out an ON/OFF control of the output transistor. A serge detecting circuit section detects a power supply serge voltage on the power supply line. A drive circuit section supplies a voltage to the gate of the output transistor from the power supply line based on an output voltage of the serge detecting circuit section when the power supply serge voltage is detected such that the output transistor is turned on.
Also, a semiconductor integrated circuit is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 11-32429). In the semiconductor integrated circuit of this conventional example, a transistor is connected with an output terminal to drives a load. A transistor control circuit controls the transistor. An overvoltage protection section sets to a conductive state when a voltage between the gate of the transistor and the output terminal is higher than a predetermined voltage, and is contained in a clamp circuit. A clamp control circuit detects a change of a control signal of the transistor control circuit and controls the operation of the clamping circuit based on the detection result.
Also, a voltage clamping circuit is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 11-41801). In this conventional example, the voltage clamping circuit is composed of a power supply, a 3-terminal constant voltage device that two of three terminals are connected between the output terminals of this power supply, and a clamping circuit connected with first or third terminals of the 3-terminal constant voltage device. In the clamping circuit, a first transistor and a first resistance are connected in serial between the first and second terminals. A second resistance is connected between a node between the first transistor and the first resistance and the gate or base of the said first transistor. A third resistance is connected between the gate or base of the first transistor and the third terminal. A control circuit is connected in parallel to a series connection of the second resistance and the third resistance.
Also, a protection device of a semiconductor device is disclosed in Japanese Laid Open Patent Application (JP-P2000-245137A). In this conventional example, a voltage clamping circuit is connected between electrodes of the semiconductor device to clamp a voltage of the semiconductor device to a rating voltage when a current of the semiconductor device is blocked off. One end of the voltage clamping circuit is connected with an output electrode of the semiconductor device directly or with a conductive cooling body coupled to the electrode through a low inductance material at the most short distance, and the other end of the voltage clamping circuit is connected with the control electrode of the semiconductor device at the most short distance.
Also, a clamping circuit is disclosed in Japanese Laid Open Patent Application (JP-P2002-151989A). In this conventional example, the clamping circuit clamps a serge voltage to protect a switching element. A clamp section clamps an input voltage when the input voltage becomes higher than a specific value. A time setting section sets the clamp section to a non-operating state when a specific time passed after the clamp section starts the clamp.
Also, a vertical-type field effect transistor is disclosed in Japanese Laid Open Patent Application (JP-P2002-343969A). In This conventional example, the field effect transistor is composed of a semiconductor substrate of a first conductive type, and a first base region of a second conductive type formed on the semiconductor substrate to have a polygon shape. A second base region of the second conductive type is formed in the first base region, has a higher concentration than the first base region and contains a plurality of diagonal sections extending from the center of the first base region to each of the top sections of the polygon. A source region of the first conductive type is shallower than the second base region and formed to be divided by the plurality of diagonal sections in the second base region. A source electrode contacts the source region. A drain electrode contacts a back surface of the semiconductor substrate and opposes the first base region through a drain region of the semiconductor substrate. The edge section of the source electrode extends to the inside of the second base region beyond the bottom of the source region.